october 2001 advanced information copyright ? alliance semiconductor. all rights reserved. ? as7c25512pfs32a as7c25512pfs36a 10/3/01; v.0.9.1 alliance semiconductor 1 of 2 2.5v 512k 32/36 pipeline burst synchronous sram features ? organization: 524,288 words x 32/36 bits fast clock speeds to 200mhz in lvttl/lvcmos fast clock to data access: 3.0/3.5/4.0 ns fast oe access time: 3.0/3.5/4.0 ns fully synchronous register-to-register operation single register ?flow-through? mode single-cycle deselect - dual-cycle deselect also available ( as7c25512pfd32a/ as7c25512pfd36a) pentium? * compatible architecture and timing asynchronous output enable control 100-pin tqfp package 119-ball bga (7 x 17 ball grid array package) byte write enables multiple chip enable s for easy expansion 2.5v core power supply 2.5v i/o operation ntd? * pipeline architecture available (as7c25512ntd32a/ as7c25512ntd36a) *pentium ? is a registered trademark of intel corporation. ntd? is a trademark of alliance semiconduc tor corporation. all trademarks mentioned in this document are the property of their respective owners. logic block diagram: pin arrangements: dqp c /nc dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c ft v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d /nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqp b /nc dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a /nc lbo a5 a4 a3 a2 a1 a0 nc nc v ss v dd a18 a17 a10 a11 a12 a13 a14 a15 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a6 a7 ce0 ce1 bw d bw c bw b bw a ce2 v dd v ss clk gwe bwe oe adsc adsp adv a8 a9 nc vdd a16 note: pins 1,30,51,80 are nc for 32 tqfp 14 20 mm 512k x 32a/36a q0 q1 512k 32/36 memory array burst logic clk clr ce address dq ce clk dq d clk dq byte write registers register dq c clk dq byte write registers dq b clk dq byte write registers dq a clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down data [35:0] 4 36/32 18 16 18 19 gwe bwe bw d adv adsc adsp clk ce0 ce1 ce2 bw c bw b bw a oe a [18:0] zz oe ft clk clk 36/32 data [31:0] lbo selection guide -200 -166 -100 units minimum cycle time 5 6 10 ns maximum clock frequency 200 166 100 mhz maximum pipelined clock access time 3.0 3.5 4.0 ns maximum operating current 280 230 150 ma maximum standby current 100 70 50 ma maximum cmos standby current (dc) 30 30 30 ma
10/3/01; v.0.9.1 alliance semiconductor 2 of 2 as7c25512pfs32a as7c25512pfs36a ? ? copyright alliance semiconductor corporation. all rights rese rved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of a lliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time withou t notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained he rein represents alliance's best data and/o r estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for poten tial customers and users, and is not intended to operate as, o r provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disc laims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringeme nt of any intellectual property righ ts, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of allian ce products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a li cense under any patent rights, copyrights, mask works rights, trademarks, or any oth er intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may re asonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems im plies that the manufacturer assumes all risk of such use and a grees to indemnify alliance against all claims arising from such use. pin configuration 119 bga top view 1234567 a v ddq aa adsp aav ddq b nc a a adsc aanc c ft aav dd aanc d dqc dqpc v ss nc v ss dqpb dqb e dqc dqc v ss ce0 v ss dqb dqb f v ddq dqc v ss oe v ss dqb v ddq g dqc dqc bwc adv bwb dqb dqb h dqc dqc v ss gwe v ss dqb dqb j v ddq v dd nc v dd nc vdd v ddq k dqd dqd v ss clk vss dqa dqa l dqd dqd bwd nc bwa dqa dqa m v ddq dqd v ss bwe v ss dqa v ddq n dqd dqd v ss a1 v ss dqa dqa p dqd dqpd v ss a0 v ss dqpa dqa r nc a lbo v dd v dd anc t nc nc a a a nc zz u v ddq tms tdi tck tdo nc v ddq note: for p/n as7c25512pfs32a, 4 of the i/o pins must be left open (n.c.)
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